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CEA Tech
PhD position - Design, simulation, fabrication and characterization of an innovative logic/memory CUBE for In-Memory-Computing
CEA Tech
CEA Tech is building on CEA Leti’s successful track record innovating for industry.
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OM TJÄNSTEN
Publicerad: 5 dagar sedan
Sista ansökningsdatum: okt 31
Plats: Grenoble, Frankrike
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PhD position - Design, simulation, fabrication and characterization of an innovative logic/memory CUBE for In-Memory-Computing

SL-DRT-19-0747

RESEARCH FIELD

Electronics and microelectronics - Optoelectronics

ABSTRACT

For integrated circuits to be able to leverage the future “data deluge” coming from the cloud and cyber-physical systems, the historical scaling of Complementary-Metal-Oxide-Semiconductor (CMOS) devices is no longer the corner stone. At system-level, computing performance is now strongly power-limited and the main part of this power budget is consumed by data transfers between logic and memory circuit blocks in widespread Von-Neumann design architectures. An emerging computing paradigm solution overcoming this “memory wall” consists in processing the information in-situ, owing to In-Memory-Computing (IMC).However, today’s existing memory technologies are ineffective to In-Memory compute billions of data items. Things may change with the emergence of three key enabling technologies, under development at CEA-LETI: non-volatile resistive memory, new energy-efficient nanowire transistors and 3D-monolithic integration. CEA-LETI received a prestigious European ERC grant to support a 5 year project and 3 new PhD students on a new project. This project will leverage the aforementioned emerging technologies towards a functionality-enhanced system with a tight entangling of logic and memory. A 3D In-Memory-Computing accelerator circuit will be designed, manufactured and measured, targeting a 20x reduction in (Energy x Delay) Product vs. Von-Neumann systems. This project that adds smartness to memory/storage will not only be a game changer for artificial intelligence, machine learning, data analytics or any data-abundant computing systems but it will also be, more broadly, a key computational kernel for next low-power, energy-efficient integrated circuits.In this context, the PhD study is about the design, simulation, fabrication and characterization of an innovative logic/memory CUBE for In-Memory-Computing.

LOCATION

Département Composants Silicium (LETI)

Laboratoire d'Intégration des Composants pour la Logique

Grenoble

CONTACT PERSON

ANDRIEU François

CEA

DRT/DCOS/SCME/LICL

CEA-letiMINATEC Campus17 rue des Martyrs38 054 Grenoble Cedex 9, France

Phone number: 04 38 78 0139

Email: francois.andrieu@cea.fr

UNIVERSITY / GRADUATE SCHOOL

Toulouse III

Génie Electrique - Electronique - Télécommunications (GEET)

START DATE

Start date on 01-10-2019

THESIS SUPERVISOR

LARRIEU Guilhem

CNRS

LAAS-CNRS (UPR8001)

7, avenue du Colonel RocheBP 5420031031 Toulouse cedex 4, France

Phone number: 0561337984

Email: guilhem.larrieu@laas.fr

« The age limit is 26 years for PhD offers and 30 years old for post-doc offers. »

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